1. Field of the Invention
The present invention relates to an optical clock distribution system in a wavelength division multiplexing (WDM) network and more particularly a system for controlling clock synchronization between optical transmission units constituting an optical communication network.
2. Prior Arts
Currently, voice and data are transmitted in various forms such as STM (Synchronous Transfer Mode), ATM (Asynchronous Transfer Mode) and IP (Internet Protocol) through an optical communication network, in which an SDH (Synchronous Digital Hierarchy)/SONET (Synchronous Optical Network) system is employed as a backbone system.
Meanwhile, as a result of ongoing explosive increase of the Internet line demand in recent years, higher bit rate (ranging from 2.5 Gbps to 10 Gbps or 40 Gbps) of TDM (Time Division Multiplexing) has been introduced in each transmission unit, and at the same time efficient utilization of transmission capacity in an optical fiber cable has been in wide and active progress by introducing a WDM (Wavelength Division Multiplexing) system.
SDH/SONET is a system in which entire transmission units constituting a network are synchronized with a master clock. This system is now adopted worldwide as an appropriate communication system for implementing high-speed digital networks.
This method has various advantages such as improved connectivity between transmission units and efficient data multiplexing/demultiplexing processing. However, a clock source is required for outputting a reference clock having extremely high accuracy, which is referred to as PRC (Primary Reference Clock) in a SDH/SONET system, to be installed as a network clock source of the highest hierarchy (for example, a standard clock constituted by a cesium Cs atomic oscillator).
FIG. 1 shows a conceptual diagram of a synchronous architecture in a network employing a highly accurate clock source.
In this FIG. 1, a synchronous configuration in a network is shown. A clock signal being output from a hierarchically highest clock source 100 having an accuracy level of PRC is distributed to each transmission unit 101, 102 as a reference clock. In the following description, this clock signal having PRC-level accuracy is simply referred to as a reference clock.
Each transmission unit 101, 102 receives the reference clock being output from clock source 100 to transfer to lower level units 103, 104 and also 105, 106. As a result, a plurality (N) of transmission units 101-10N in the network are entirely synchronized with one reference clock, thus constituting a synchronous system.
Thus, in the SDH/SONET system, each transmission unit normally extracts a timing signal from data received through an optical fiber cable so as to synchronize with the reference clock.
Each transmission unit then regenerates a clock in a PLL circuit provided therein, to transmit data to a succeeding transmission unit. Namely, a transmission unit regenerates a clock from a received data and then forwards a data including a clock signal to a succeeding unit.
Here, in the SDH/SONET system, performance is required in each transmission unit on how precisely the reference clock is to be transferred throughout the entire network maintaining the quality of the reference clock between the transmission units.
In order to cope with this requirement, in the conventional SDH/SONET system, one method shown in FIG. 2 is known as a means for transferring the reference clock originated from clock source 100 to each transmission unit. The method is as follows.
First, a clock of PRC-level accuracy being output from clock source 100 is input as an external reference clock (EXT CLK) into an SDH transmission unit 101 provided in a master station. A PLL circuit provided in SDH transmission unit 101 generates a unit master clock MCLK-1. SDH transmission unit 101 outputs a transmission data to a succeeding transmission unit 102 using the unit master clock MCLK-1.
Similarly, in SDH transmission unit 102, after a timing component is extracted from the received data, a PLL circuit provided in SDH transmission unit 102 generates a unit master clock MCLK-2. SDH transmission unit 102 outputs a transmission data to a succeeding SDH transmission unit 103 using the unit master clock M-CLK2.
In such a way, each plurality of SDH transmission units 101-10N transfers the reference clock originated in clock source 100 one after another, and thus the synchronization can be established throughout the entire network.
Here, in the standardized recommendations/regulations by ITU-T/BELLCORE or the like, there have been settled severe specifications in regard to the reference clock quality for transfer. A reference clock of PRC-level clock originated from clock source 100 is to be relayed in 20 SDH transmission units maximum, and each SDH transmission unit is to regenerate the clock to output using a PLL circuit provided therein.
In addition, one clock source 100 is normally provided for generating the reference clock to output. However, considering a possible failure of clock source 100, a standby (protection) clock source is often provided on the opposite transmission unit side (on the transmission unit 10N side) thus constituting a redundant configuration.
Also, although a network of linear configuration is shown in FIG. 2, a similar method to the above may be applied in a network of ring (circle-shaped) configuration to transfer a PRC-level reference clock, i.e. a master clock generated from clock source 100.
Here, as a property of such networks, as the number of SDH transmission units for repeating the reference clock from clock source 100 increases, the number of PLL circuits transferring the clock also increases, which results in deterioration in the reference clock quality. In ITU-T recommendations, considering the aforementioned effect, the maximum number of repeating units is specified to limit to 20, as mentioned earlier. Also, there is specified a requirement to provide a clock regeneration unit to suppress jitters and wanders for succeeding transmission exceeding the abovementioned limit. Further, the number of these clock regeneration units is specified up to 10.